Browse Prior Art Database

Bubble Chip Configuration

IP.com Disclosure Number: IPCOM000086774D
Original Publication Date: 1976-Oct-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Ashar, KG: AUTHOR [+2]

Abstract

A bubble chip configuration suitable for use with a single-level-metallurgy (SLM) Y-I bar switch is described. This configuration overcomes the known problem of data reversal that Y-I bar switches have.

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Bubble Chip Configuration

A bubble chip configuration suitable for use with a single-level-metallurgy (SLM) Y-I bar switch is described. This configuration overcomes the known problem of data reversal that Y-I bar switches have.

A schematic diagram of the bubble chip configuration is shown below in which the T-I bar shift register is designated by an arrow with a circle on the side of the arrow corresponding to the stem side of the Y elements.

(Image Omitted)

As shown in the figure, the generator 10 generates bubbles which propagate down the write channel 12. The write channel 12 interfaces with an idler loop 14 through transfer gates (not shown) which have the same periodicity as the transfer gates (not shown) that interface with the minor loops 16 A,B,C,D. Idler loop 14 then interfaces with the minor loops 16 A,B,C,D through transfer gates (not shown). Transfer between the write channel 12 and the idler loop 14 is by the same algorithm (transfer 1 bubble, transfer 2 bubble, etc.) as the transfer into the minor loops 16 A,B,C,D. The bubbles are transferred from minor loops 16 A,B,C,D by transfer gates (not shown) to read channel 18. The bubbles propagate down the read channel 18 to detector 20.

To track the operation, consider the transfer of two bubbles per minor loop. The bubbles are generated in order 0 1 2 3 4 5 6 7 and propagated up the write channel 12. After transfer to the idler loop 14, they are in order 6 7 4 5 2 3 0 1.

The bubbles are then propagated...