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Read Channel Test Circuit

IP.com Disclosure Number: IPCOM000086793D
Original Publication Date: 1976-Oct-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Sierra, HM: AUTHOR

Abstract

This circuitry tests and qualifies a digital magnetic recording read channel by electrically generating a signal simulating that obtained from a read head, but without the problems created by a mechanical drive, read and write heads and/or tape (or disk) surface.

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Read Channel Test Circuit

This circuitry tests and qualifies a digital magnetic recording read channel by electrically generating a signal simulating that obtained from a read head, but without the problems created by a mechanical drive, read and write heads and/or tape (or disk) surface.

A digital signal from a word generator or computer is passed by OR gate 1 to a bessel filter 2 having an impulse response equal to the sensitivity of read head
3. The signal is passed from filter 2 through differentiator 4 and attenuator 5 to phase splitter 6. Splitter 6 provides an analog signal in parallel to the leads 7 and 8 of read channel 9 connected to input and output terminals of read head 3, thus providing a means for applying a simulated test signal to the read channel in bypass of the read head. The test signal thus generated is passed through preamplifier 10, differentiator/low-pass filter 11 with requisite step response, and sense amplifier 12 to digital clocking and detection circuits (not shown).

Since read-back is linear, the circuitry must operate in linear mode. To avoid signal distortion, the phase response of the circuitry must be linear within the frequency band of interest.

Assume a write waveform with binary pulses of 0 and +5V levels, phase- encoded (PE) recording, 1600 bpi, tape speed of 50 in/sec, maximum read-back pulse of 8 mV peak-peak, and a read-back signal with a 6 dB dynamic response. With PE, f1 (the lowest frequency of the read waveform) is ob...