Browse Prior Art Database

Data Staging Controls

IP.com Disclosure Number: IPCOM000086844D
Original Publication Date: 1976-Nov-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 34K

Publishing Venue

IBM

Related People

Hart, CW: AUTHOR [+4]

Abstract

Queue control block (QCB) pointers are inserted and activated to and from a collapsing action FIFO (first in, first out) queue. The control is for the staging memory system which includes a mass memory, which stages data to a buffer memory and receives destaged data from the buffer memory. The control that is programmed, which programming includes a QCB Scan that alerts a FIFO Queue Handler program for the QCBs that a given QCB pointer needs to be inserted into one of the several FIFO queues. A stage scheduler program module controls the mass storage system for staging data signals from the mass memory to the buffer memory. This program module also activates QCBs from the FIFO queues.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 3

Data Staging Controls

Queue control block (QCB) pointers are inserted and activated to and from a collapsing action FIFO (first in, first out) queue. The control is for the staging memory system which includes a mass memory, which stages data to a buffer memory and receives destaged data from the buffer memory. The control that is programmed, which programming includes a QCB Scan that alerts a FIFO Queue Handler program for the QCBs that a given QCB pointer needs to be inserted into one of the several FIFO queues. A stage scheduler program module controls the mass storage system for staging data signals from the mass memory to the buffer memory. This program module also activates QCBs from the FIFO queues. Additionally, the control has a QCB FIFO Queue Handler which controls the queue table for inserting and deleting QCB pointers in the collapsing action FIFO queues.

In one version, the QCB FIFO Queue Handler provides a stage scheduler with four FIFO queues, 0 to 3. These independent FIFO queues relate to corresponding independent portions of the mass memory. The table indicates the queue setup. Each entry in the table is byte wide, having 6 bits of offset to the QCB for the respective portion of the mass memory. Two of the bits in each byte are QCB recovery bits which are always set to zero after a restore initial microprogram load (IMPL). If a restore IMPL occurs, verification of the control for the staging memory, includes moving the outstanding QCBs from the buffer memory and inserting such into the appropriate QCB tables of the control. This is done in the manner that the FIFO queues of the control do not contain the restored QCBs. The affect of this is nonactivatable QCBs. Since there is no reference to such QCBs in the buffer memory that are now contained in the control. Therefore, the control must initialize the FIF...