Browse Prior Art Database

High Density Memory Cell Fabrication

IP.com Disclosure Number: IPCOM000086848D
Original Publication Date: 1976-Nov-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 67K

Publishing Venue

IBM

Related People

Coady, J: AUTHOR

Abstract

This describes a unique process for fabricating high-density single-cell memories.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

High Density Memory Cell Fabrication

This describes a unique process for fabricating high-density single-cell memories.

Referring to the figures, the specific sequence of steps for forming the structure is as follows:

A substrate 10 formed of boron-doped single-crystal silicon is oriented, cut, lapped, polished and coated with a 2500 angstrom thick layer of arsenic doped oxide 11 formed by any convenient technique. Over this layer of doped oxide there is deposited, in a chemical-vapor-deposition furnace, a second 2500 angstrom thick layer of oxide 12. Once these oxide layers 11 and 12 are formed, a photoresist layer (not shown) is deposited over the layers 11 and 12 which are then delineated into specific regions 13, 14 and 15.

Once these regions are suitably delineated, the wafer is heated to a temperature of approximately 900 to 1000 degrees C and the arsenic in the oxide layer 11 is permitted to diffuse into the semiconductor body to form diffusions 16, 17 and 18. As diffusions 16, 17 and 18 form, a thin oxide layer 19 is also formed on the surface of the exposed semiconductor around the regions 13, 14 and 15. Following this step, the regions 13 and 15 are again masked in the conventional manner with photoresist and the oxide region 14, as well as the surrounding layers 19 of silicon dioxide, removed by again using a suitable etch which will attack the silicon dioxide layers.

Following the removal of the region 14 and layer 19, a plate oxide 20 (Fig. 2) is formed over the surface of the semiconductor body by utilizing the well-known thermal dry cycle and is grown to a thickness of between 450 and 500 angstroms. Preferably oxide 20 is grown in a hydrochloric-acid environment to improve the quality of the oxide layer 20. Following this creation of layer 20, a uniformly 1500 angstrom thick polysilicon layer 21 is formed over the entire surface of the device. On top of polysilicon 21 there is formed a thin 100-150 angstrom thick layer 22 of silicon nitride. Following the creation of this silicon nitride layer 22, a 2000 angstrom thick layer 23 is formed by a chemical vapor deposition technique over the surface of the silicon nitride layer 22.

Once these layers have been uniformly deposited over the semiconductor device, still another photoresist etching operation is performed. Such photoresist etching is conducted in the same manner as previously described. However, in this instance the layers 21, 22 and 23 are removed everywhere except over the defined storage diffusion 17. The silicon oxide layer 23 is removed in the conventional fashion and a hot phosphoric acid solution is utilized to remove the silicon nitride layer 22. Finally, the polysilicon layer 23 is removed utilizing again a well-known silicon etch which may be, for example, a mixture of hydrofluoric, nitric and acetic acids. Preferably, the particular sequence is as follows:

The entire layer is coated with a photoresist layer and the regions to be saved are defined by...