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Redundancy by Overlaying Partially Good Arrays

IP.com Disclosure Number: IPCOM000086850D
Original Publication Date: 1976-Nov-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Kotorman, L: AUTHOR

Abstract

This describes an effective redundancy repair technique by the logical union or overlay of two partially good arrays in order to obtain an apparently good array. It can be especially used with arrays which are susceptible to failure mechanisms causing polarity cell failure, and will provide a self-healing feature when the dominant failure mechanism is affecting a population of cells, in which failure is not detectable initially but may deteriorate with time.

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Redundancy by Overlaying Partially Good Arrays

This describes an effective redundancy repair technique by the logical union or overlay of two partially good arrays in order to obtain an apparently good array. It can be especially used with arrays which are susceptible to failure mechanisms causing polarity cell failure, and will provide a self-healing feature when the dominant failure mechanism is affecting a population of cells, in which failure is not detectable initially but may deteriorate with time.

The circuit shown in the figure is especially useful in those arrays in which an inversion occurs between the cell and the output data. In such cells the inversion is present from the nondirect side of the array, and there is no inversion if the integrated cell is located on the output side of the sense latch. Such data inversion causes difficulty which can be overcome by the logic circuit in the figure. This circuit produces the required inversion corresponding to the integrated side of the arrays.

The figure shows two arrays 10 and 11 the output of which is received on respective lines 12 and 13. Line 12 in turn feeds information through parallel inverters 14 and 15 to respective NAND circuits 16 and 17. Similarly, the data output line 13 is fed through a first inverter 18 to a NAND circuit 19 and through a second parallel inverter 20 to NAND circuit 17. The high-order word address bit is fed into the NAND circuits 16 and 19 together with the inputs from the li...