Browse Prior Art Database

Binary Divide Mechanism

IP.com Disclosure Number: IPCOM000086852D
Original Publication Date: 1976-Nov-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 4 page(s) / 49K

Publishing Venue

IBM

Related People

Chiu, PC: AUTHOR [+3]

Abstract

A binary divide mechanism is described for performing fixed-point and floating-point divide operations in a microprogrammed data processor. The mechanism includes hardware for enabling the subtraction/restoration method of division to be accomplished in a more rapid manner. In particular, the adding of a relatively small amount of additional hardware to the processor data flow enables each subtraction/restoration loop to be completely performed in a single microword cycle.

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Binary Divide Mechanism

A binary divide mechanism is described for performing fixed-point and floating-point divide operations in a microprogrammed data processor. The mechanism includes hardware for enabling the subtraction/restoration method of division to be accomplished in a more rapid manner. In particular, the adding of a relatively small amount of additional hardware to the processor data flow enables each subtraction/restoration loop to be completely performed in a single microword cycle.

As is known, the subtraction/restoration method is performed by initially left-aligning both the dividend and divisor. The divisor is then subtracted from the dividend. If the difference is positive or zero, the quotient bit is one and the difference is the remainder.

If the difference is negative, the quotient bit is zero and the divisor is added back to the difference to form the remainder. In either case, the remainder is then left shifted one bit position and becomes the new dividend. This process is repeated until the remainder becomes zero or the desired number of quotient bits is obtained.

In prior implementations, several microword cycles were required to perform each repetition of the subtraction/restoration operation. With the mechanism described herein, execution of a single microword, called a "divide microword", enables the processor to perform the subtraction, the testing of the result, the adding back of the divisor (if necessary), the one-bit left shift of the remainder and the quotient bit generation. all in one microword cycle. Repeat execution of this divide microword will perform a binary divide machine instruction.

With reference to the drawing, the dividend and divisor fields are initially left- aligned or left-justified and a preliminary test is performed to determine that the quotient will not be too big to fit into the quotient field in the result. In particular, the divisor field is subtracted from the left part of the dividend field, which is of the same length as the divisor field. If the difference is positive or zero, the quotient will be too big and a fixed-point divide exception is generated. Assuming that the quotient will not be too big (no divide exception), then the left-aligned dividend field is loaded into a destination register 10 and the left-aligned divisor field is loaded into a register in a local store 11. A quotient register 12 is reset to zero and a loop counter 13 is set to the number of divide microword cycles that are required. The number of such microword cycles is equal to the number of bit positions (including leading zeros) that will appear in the quotient field, this number being specified by the processor architecture requirements.

With these preliminary matters accomplished, the first divide microword is issued to perform the first subtraction/restoration operation. As a first step in this microword cycle, the local store 11 is accessed (per address in local store address register (L...