Browse Prior Art Database

Fast Action Control Gate Generator

IP.com Disclosure Number: IPCOM000086854D
Original Publication Date: 1976-Nov-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Bruetsch, BJ: AUTHOR [+2]

Abstract

A fast-action control gate generator is described for generating gating signals having leading and trailing edges which are precisely coincident with the leading edges of successive clock pulses. This generator is useful in connection with data processor control circuitry having critical timing requirements.

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Fast Action Control Gate Generator

A fast-action control gate generator is described for generating gating signals having leading and trailing edges which are precisely coincident with the leading edges of successive clock pulses. This generator is useful in connection with data processor control circuitry having critical timing requirements.

Fig. 1 shows the desired timing relationships. In particular, it shows an operating cycle which is subdivided into four clock intervals T0-T3. These intervals are established by clock pulses T0-T3, with only the clock pulses T0 and T2 being shown. It is desired to generate a first gating signal, designated as control gate A, having a leading edge which is precisely coincident with the leading edge of clock pulse T0 and a trailing edge which is precisely coincident with the leading edge of clock pulse T2. It is also desired to generate a second gating signal, designated as control gate B, having a leading edge which is precisely coincident with the leading edge of clock pulse T2 and a trailing edge which is precisely coincident with the leading edge of the next T0 clock pulse. Though only one complete cycle is shown in Fig. 1, it is to be understood that each of the waveforms is repetitive in nature.

Fig. 2 shows the construction of the control gate generator. Each T0 clock pulse is supplied by way of NAND circuit 10 and driver circuit 11 to set a latch circuit 12. Each T2 clock pulse is supplied by way of NAND circuit 13 and driver circuit 14 to reset the latch circuit 12. If the timing were not critical, the outputs of latch circuit 12 could be used as the control gate signals. Unfortunately, some time delay is ex...