Browse Prior Art Database

Control Store Branch Mechanism

IP.com Disclosure Number: IPCOM000086855D
Original Publication Date: 1976-Nov-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 41K

Publishing Venue

IBM

Related People

Dvorak, TJ: AUTHOR [+2]

Abstract

A control store branch mechanism is described for use in a microprogrammed data processor for enabling microcode branching over a wider range of control store address values than is normally possible with microwords of a given length.

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Control Store Branch Mechanism

A control store branch mechanism is described for use in a microprogrammed data processor for enabling microcode branching over a wider range of control store address values than is normally possible with microwords of a given length.

Machine instructions are executed by reading microwords out of a control storage portion 10a of a storage unit 10. The microwords are read out one at a time. Each microword is set in a control register 11 and decoded by a decoder
12. Each microword establishes a microword cycle and the resulting control signals from decoder 12 serve to control the data flow buses and functional units in the processor to accomplish the data movement and manipulation specified by such microword.

The addressing of control store 10a is accomplished by storage address register (SAR) 13. Since SAR 13 is also used to address the main storage portion 10b, each control store address set in SAR 13 is also set in a buffer address register (BAR) 14. For the case of a nonbranch microword, the address for the next microword is normally obtained by incrementing the address in BAR 14 by incrementer 15 and then setting the incremented address in SAR 13. This same procedure is followed for the case of branch-type microwords except that, if the branch is to be taken, some of the hits in SAR 13 are set instead by branch address hits obtained from the microword in control register 11 by way of branch address lines 16.

From the foregoing, it is seen that the maximum possible range of control store branch addresses is limited by the length of the microwords. In fact, since some bits in each microword are needed to identify the microword, less than the full microword length is available for branch address purposes. Assume, for example, that each microword has a length of 16 bits and that a maximum of 12 bits are available for specifying a branch address. This means that, at best, the branch address cannot be more than 4096 address locations removed from the address of the branch microword which causes the branch. This unduly restricts the branching range.

It is assumed that the control store 10a has 128K addressable storage locations, that the microword length is 16 bits and that the maximum number of bits available for branch addresses is 12 bits. Despite this 12-bit limitation on the microword branch address, the mechanism described herein allows microcode branching to any control store address in the 128K control store without limitation.

This desirable result is accomplished by implementing a new microword called "Branch High/Low". When used, this branch High/Low microword is immediately followed by either a 16-bit address constant (ADCON) microword or a 16-bit data constant (DC) microword. One bit in the Branch High/Low microword, for example, bit 15, is used to indicate either a branch high condition or a branch low condition. If this assumed bit, namely, bit 15, has a value of on...