Browse Prior Art Database

Isolation Procedure for Stuck Latch Defects in Shift Registers

IP.com Disclosure Number: IPCOM000086858D
Original Publication Date: 1976-Nov-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 59K

Publishing Venue

IBM

Related People

Hermann, AL: AUTHOR [+3]

Abstract

Certain electronic package assemblies employ long shift register (SR3 strings spanning many components. Each such string is brought to the I/Os of the package carrying the components (Fig. 1). The application of detailed functional tests depends on the ability to scan appropriate bit data into the individual latches from the primary scan input and scan out the data captured in these latches at the scan primary output. Hence, it is required to test and verify each SR string on the package before proceeding to apply the functional tests. Certain common failure modes in standard latch designs manifest themselves as a "stuck-latch" defect. This is characterized by the inability to change the state of that latch through the scan operation.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 3

Isolation Procedure for Stuck Latch Defects in Shift Registers

Certain electronic package assemblies employ long shift register (SR3 strings spanning many components. Each such string is brought to the I/Os of the package carrying the components (Fig. 1). The application of detailed functional tests depends on the ability to scan appropriate bit data into the individual latches from the primary scan input and scan out the data captured in these latches at the scan primary output. Hence, it is required to test and verify each SR string on the package before proceeding to apply the functional tests. Certain common failure modes in standard latch designs manifest themselves as a "stuck-latch" defect. This is characterized by the inability to change the state of that latch through the scan operation. This disclosure details a heuristic procedure to do speedy diagnosis of such a latch defect detected in a shift register string.

Fig. 1 shows a shift register configuration with many latches. The functioning of the string can be explained with the use of Fig. 2. The data-in lines are the outputs of the random logic segments (RLS) in the design. Data on these lines are captured into the latches by the application of the data clocks. Similarly, data at the scan-in lines can be transferred into the latches by applying the scan-in clock. Application of the scan-out clock makes the data available at the latch outputs. Each latch output feeds other logic segments and the scan input of the next adjacent latch.

In order to load the SR string with any desired bit pattern, each bit is presented at the primary scan input, and the scan-in and scan-out locks are applied sequentially. This is the scan in operation. To inspect the contents of the SR string, the primary scan output is sampled after each application of the scan-in and scan-out clocks. During functional testing stimuli are first applied by scanning in the appropriate bit pattern, the outputs of RLS are...