Browse Prior Art Database

MTL T/2/L Parallel Clock Powering

IP.com Disclosure Number: IPCOM000086886D
Original Publication Date: 1976-Nov-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Robbins, GJ: AUTHOR

Abstract

This is a method of distributing logic signals requiring high fanout (e.g., clock powering trees) to merged transistor logic (MTL) gates on chip with a minimum of delay, signal skew, circuit and wiring overhead.

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MTL T/2/L Parallel Clock Powering

This is a method of distributing logic signals requiring high fanout (e.g., clock powering trees) to merged transistor logic (MTL) gates on chip with a minimum of delay, signal skew, circuit and wiring overhead.

In the above figure, a Schottky T/2/L gate is used to receive signals which will be widely distributed. The signals can emanate from other T/2/L logic gates on chip or directly from offchip. This T/2/L gate is powered by a +1.6V supply and a ground power supply. The output of the T/2/L gate (at point B) can be dotted with other T/2/L outputs to perform the AOI (AND-OR Invert) Logic function. This output signal can be distributed to a large MTL fan-in via a single signal line.

At each MTL input, an isolated Schottky diode is provided for logical isolation of functions. The MTL logic on chip is connected to the power supplies such that the most negative power supply potential is derived by the collective diode action of the MTL circuit. This results in the circuit having a switching threshold 0.85 volt higher than conventional implementation. This allows the utilization of the Schottky diode on input without degradation of signal-noise margin.

0ther MTL logic signals may be logically combined with the signal emanating from the T/2/L powering gate(s) at point C.

Signal translation from MTL to T/2/L may also be performed. This is accomplished by using the components of the T/2/L gate in a different manner to form the converte...