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Browse Prior Art Database

MTL Exclusive OR Circuit

IP.com Disclosure Number: IPCOM000086887D
Original Publication Date: 1976-Nov-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Robbins, GJ: AUTHOR

Abstract

This circuit performs a merged transistor logic (MTL) compatible exclusive 0R (XOR) function. The equivalent function implemented in MTL requires six logic gates and three levels of logic. The unit logic function requires six units of powering (lateral PNP current sources), whereas three units are required for this circuit. Hence, this circuit dissipates 50% of the power of the conventional implementation, and offers almost a three-times improvement in performance.

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MTL Exclusive OR Circuit

This circuit performs a merged transistor logic (MTL) compatible exclusive 0R (XOR) function. The equivalent function implemented in MTL requires six logic gates and three levels of logic. The unit logic function requires six units of powering (lateral PNP current sources), whereas three units are required for this circuit. Hence, this circuit dissipates 50% of the power of the conventional implementation, and offers almost a three-times improvement in performance.

This circuit comprises (1) an isolated collector diffusion containing two normally operated transistor devices sharing a common collector, each having integral Schottky diodes to prevent saturation, (2) two pull-up devices which may be either resistors or lateral PNP current sources and (3) an MTL logic gate.

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