Browse Prior Art Database

Multiple System Clocked Shift Register Latch

IP.com Disclosure Number: IPCOM000086894D
Original Publication Date: 1976-Nov-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Eichelberger, EB: AUTHOR [+3]

Abstract

Described is a simple technique which allows multiple system clocks to control the acquisition of system data by level system scan design (LSSD) shift register latch (SRL) techniques, as disclosed in U. S. Patent 3,783,254.

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Multiple System Clocked Shift Register Latch

Described is a simple technique which allows multiple system clocks to control the acquisition of system data by level system scan design (LSSD) shift register latch (SRL) techniques, as disclosed in U. S. Patent 3,783,254.

As depicted in the drawing, one or inputs are added to the physical macro SRL. This input serves as the clock input for additional C clocks and may be left floating, if not used. Additional system data ports are constructed from regular logic gates external to the physical macro SRL. These gates are then connected to the SRL extend input. Hence, if the multiple system clocks are not needed, the SRL automatically reverts back to a single system clock SRL.

Therefore, multiple physical macro SRL support (for multiclocked SRLs), which has both layout, wiring rules and support service ramifications, as well as engineering change impact upon chip image macros, is not needed. Also, the logical functionality of the basic building block sequential element for LSSD design is enhanced.

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