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Tie Break and Allegiance Network

IP.com Disclosure Number: IPCOM000086896D
Original Publication Date: 1976-Nov-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 65K

Publishing Venue

IBM

Related People

Antanaitis, BC: AUTHOR [+3]

Abstract

This network provides the capability of "tie breaking" in the processing of possibly simultaneous requests from a plurality of processors for the exclusive use of a shared facility. Nonsimultaneous requests are serviced on a first come - first serve basis. Allegiance to the selected processor (if requests are simultaneous) and to the first processor to request service (if requests are nonsimultaneous) is maintained after service begins until completion of the requested service is acknowledged by the processor.

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Tie Break and Allegiance Network

This network provides the capability of "tie breaking" in the processing of possibly simultaneous requests from a plurality of processors for the exclusive use of a shared facility. Nonsimultaneous requests are serviced on a first come - first serve basis. Allegiance to the selected processor (if requests are simultaneous) and to the first processor to request service (if requests are nonsimultaneous) is maintained after service begins until completion of the requested service is acknowledged by the processor.

Microprocessor 1 and another processor, such as, for example, a computer channel 2, are adapted to each other by adapter 3, as shown in Fig. 1. Adapter 3 includes a number of shared facilities, such as registers 40, which are used on occasion by each of the processors 1 and 2, e.g., when each processor transmits data to the other.

Assuming that channel 2 is about to send data to processor 1, tag line 4 is raised triggering control circuits 5 to issue a request signal on line 6 which is latched by trap latch 7. The latching of trap latch 7 degates (turns off), via line 8, trap latch 9, precluding the latching of the latter in response to any subsequent signal on input line 10.

Trap latches 7 and 9 are shown in Fig. 2, latch 9 differing from latch 7 solely by the additional output 11 from AND circuit 12. In response to the latching of trap latch 7, line 13 falls degating AND circuit 14 (Fig. 1). After a short delay through 0R circuit 15, line 16 is raised, and after a somewhat longer delay (provided by delay 17), n line 18 falls. Line 11 remains raised in response to the earlier degating of trap latch 9.

AND circuit 14 produces a "channel OK" signal on line 19 as soon as the inputs 13 and...