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Cyclic Redundancy Check for SDLC Architecture

IP.com Disclosure Number: IPCOM000086897D
Original Publication Date: 1976-Nov-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 40K

Publishing Venue

IBM

Related People

Breslau, FC: AUTHOR [+2]

Abstract

IBM synchronous data link control (SDLC) architecture specifies that all messages (frames) from a primary station or a terminal will be preceded and followed by a framing character (bit pattern 0 111 111 0) called a flag or F byte. The F byte will not be allowed as a regular data byte or as part of the message. Thus, in order to transmit more than five contiguous 1 bits as part of a message, the transmitter of a message will follow every fifth consecutive 1 bit with one 0 bit. The receiver will automatically take out every 0 bit preceded by five 1 bits. This "bit stuffing/destuffing" allows for data integrity. To provide error detection, a cyclic redundancy check (CRC) is performed on all data bits following the F byte with the exception of the "stuffed/destuffed bits".

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Cyclic Redundancy Check for SDLC Architecture

IBM synchronous data link control (SDLC) architecture specifies that all messages (frames) from a primary station or a terminal will be preceded and followed by a framing character (bit pattern 0 111 111 0) called a flag or F byte. The F byte will not be allowed as a regular data byte or as part of the message. Thus, in order to transmit more than five contiguous 1 bits as part of a message, the transmitter of a message will follow every fifth consecutive 1 bit with one 0 bit. The receiver will automatically take out every 0 bit preceded by five 1 bits. This "bit stuffing/destuffing" allows for data integrity. To provide error detection, a cyclic redundancy check (CRC) is performed on all data bits following the F byte with the exception of the "stuffed/destuffed bits".

Since a message can be of unknown length, SDLC requires that a CRC checker, preset to a known value before message reception began, will go to another known value before the trailing F byte of the message. This is ensured by appending a fixed number of known bits, referred to as CRC bits, to the message. SDLC uses a 16 bit CRC. Normally, it is expected that an eight bit register is used to buffer the CRC checker so that if the register contains an F byte, the CRC checker is immediately checked to see if it contains the correct value for a valid frame. A unique method for checking CRC without using this buffer/register is described below.

Since the CRC checker uses destuffed messages, a destuffer is required in series between the buffer and the CRC checker. Since the destuffer is basically a three bit counter, it can detect 5 contiguous one bits and look at the following bit. If this bit is a "0", it is a stuffed bit. If it is a "1", it may be an F byte. The next bit must Be a zero for a F byte. If it is another "1", (0 111 111 1) this is an illegally defined sequence and the frame should be discarded. Since there is no serial register, the first six or seven bits of the F byte ca...