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Determining Oxide Thickness in MOSFET Technologies

IP.com Disclosure Number: IPCOM000086909D
Original Publication Date: 1976-Nov-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 41K

Publishing Venue

IBM

Related People

Beilstein, KE: AUTHOR [+2]

Abstract

One of the fundamental parameters in IGMOSFET device characteristics is the thin gate oxide thickness since it effects the turn-on voltage, transconductance and capacitance of the device. A method is disclosed to measure oxide thickness which leads to the characterization of the field-effect transistor (FET) in terms of fundamental parameters such as oxide charge density, doping concentration and surface mobility. The measurement provides values of oxide thickness information for individual wafers or sites, which is needed to obtain a statistical data base of the fundamental parameters. A metal oxide semiconductor (MOS) capacitance measurement is made on the kerf of the wafer after the wafer has been processed, using a DC parametric tester.

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Determining Oxide Thickness in MOSFET Technologies

One of the fundamental parameters in IGMOSFET device characteristics is the thin gate oxide thickness since it effects the turn-on voltage, transconductance and capacitance of the device. A method is disclosed to measure oxide thickness which leads to the characterization of the field-effect transistor (FET) in terms of fundamental parameters such as oxide charge density, doping concentration and surface mobility. The measurement provides values of oxide thickness information for individual wafers or sites, which is needed to obtain a statistical data base of the fundamental parameters. A metal oxide semiconductor (MOS) capacitance measurement is made on the kerf of the wafer after the wafer has been processed, using a DC parametric tester.

Fig. 1 shows an external known reference capacitor 2 in series with the gate 4 of a small monitor FET 6. The gate 8 of a large FET 10, with its source and drain diffusion grounded, is also connected at this node. The large FET 10 with source/drain grounded is effectively a MOS capacitor.

When a two-step pulse 12 is applied to the input node, the first pulse V(A1) will turn both the FETs on to give an equivalent circuit of Fig. 2, and removes the device 10 from the nonlinear capacitance region. Since a voltage V(G1) appears at the gate, the monitor FET 6 is turned on to give current I(DS1). The second pulse has a magnitude V(A2) which increases the gate bias to V(GS2) and correspondingly the monitor FET 6 current to I(DS2). The second pulse is of interest in measuring the device 10 capacitance. The step (V(A2)-V(A1)) is divided between C(REF) and C(TOTAL) = (C(STRAY2) + C(OX) + C(MONITORFET)), which gives the voltage (V(GS2)-V(GS1)). I(DS1) and I(DS2) can easily be measured. Knowing the device 6 characteristics, the unknowns V(GS2) and V(GS1) can be determined. Knowing all the voltages and values of C(REF), one can solve for C(OX). C(TOTA...