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Relating Logic Design to Physical Geometry in LSI Chip

IP.com Disclosure Number: IPCOM000086910D
Original Publication Date: 1976-Nov-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 4 page(s) / 135K

Publishing Venue

IBM

Related People

Lallier, KW: AUTHOR [+2]

Abstract

LSI chip designs are assembled from a library of standard circuits. Each circuit is described in the library by physical geometry, i.e., diffusions, gates, contacts and the like used to embody the circuit in a chip. The quality of a design is measured by subjecting the design logic to fault simulation, testing and diagnostics before commitment to manufacture. By appropriately tracing the physical geometry, a logic model may be derived that provides more meaningful and accurate quality measurement than the conventional logic model. The derived logic models also identify sneak paths, shorts and redundant logic in the design before manufacture. Test coverage of the design has greater significance when using the derived logic model as compared to the conventional logic model.

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Relating Logic Design to Physical Geometry in LSI Chip

LSI chip designs are assembled from a library of standard circuits. Each circuit is described in the library by physical geometry, i.e., diffusions, gates, contacts and the like used to embody the circuit in a chip. The quality of a design is measured by subjecting the design logic to fault simulation, testing and diagnostics before commitment to manufacture. By appropriately tracing the physical geometry, a logic model may be derived that provides more meaningful and accurate quality measurement than the conventional logic model. The derived logic models also identify sneak paths, shorts and redundant logic in the design before manufacture. Test coverage of the design has greater significance when using the derived logic model as compared to the conventional logic model. Typically, the number of faults to be simulated is reduced by the derived logic as compared to the conventional logic model when a fault assignment mode is selected to test the design.

Defensive Publication T9C4,007, published March 2, 1976, by the U.S. Patent and Trademark Office, describes a library of standard circuits and their related physical geometry for incorporation into a chip. The publication also describes a method of tracing the physical geometries of a logic circuit. The present disclosure is directed to partitioning the logic design into a plurality of unique circuit paths. Each path is formed from different physical geometries which operate as an "AND" function since all must be operable in order for the path to function. All such unique paths act in parallel as a logical "OR" since any one path is sufficient to switch the circuit. The derived logic model may be exercised by providing test patterns to the "AND" function and comparing the output of the "OR" function with the expected result.

Fig. 1 shows a physical layout in an LSI chip design for the following function. F = (A+B) x C DxE (1).

The geometry elements making up each path includes simple conductive elements comprising diffusion paths labeled Gn where n is an integer and metal gates labeled A...N.

Fig. 2 shows a matrix of the geometries forming the various paths, between the voltage bus and the ground bus, for the layout shown in Fig. 1. Each section of geometry is appropriately identified with orthogonal coordinates, and tabulated according to path with coordinates of contiguous geometries having a corresponding coordinate. Each circuit path through the logic function can be identified by conventional data processing techniques. The logic function can be simulated from the synthesized logic model with a significant reduction in malfunctions to be simulated. More important, the actual physical design identifies "sneak" paths through the physical geometry which adds significance to the testing of a physical design for a logic function.

Fig. 3 describes the process for defining the discrete circuit paths between the voltage bus and gr...