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Logical To Real Register Address Mapping

IP.com Disclosure Number: IPCOM000086914D
Original Publication Date: 1976-Nov-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Related People

Franklin, JW: AUTHOR

Abstract

The architecture for any digital computer system defines a set of machine states, which may be represented in register contents and status words from which it is possible to detect the exact state of the machine at any point in time.

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Logical To Real Register Address Mapping

The architecture for any digital computer system defines a set of machine states, which may be represented in register contents and status words from which it is possible to detect the exact state of the machine at any point in time.

The machine state may be implemented, in part, by general purpose registers. Some computer systems only provide one set of general-purpose registers, the use of which is switched between application programs and operating-systems programs. Performance may be improved by providing additional sets of registers, thus precluding the need to always store/ restore the general purpose registers when going to/from the application program state.

A method is described in which a computer system may have eight sets of sixteen registers. The sets are provided for. 1. Problem state 2. Supervisor state 3. SVC (Supervisor call) handler in supervisor state 4. SVC handler in problem state 5. I/O handler in supervisor state 6. I/O handler in problem state
7. Exception handler in supervisor state 8. Exception handler in problem state.

The general purpose registers in the eight sets are addressed by an eight-bit R operand field.
1. The leftmost four bits in the eight-bit R address are set by

the state of certain bits in the program status word (PSW) of

the machine, as follows:

a. Bit 3 is set to the inverse of the problem state bit in

the PSW.

b. Bit 2 is set to one if the supervisor call new PSW is the

current PSW. Otherwise, bit 2 is set to zero.

c. Bit 1 is set to one if the I/O interruption new PSW is

the current PSW. Otherwise, bit 1 is set to zero.

d. Bit 0 is set to one if the program interruption new PSW

is the current PSW. Otherwise, bit 0 is set to zero.
2. The generated eight-bit R address selects the real hardware

register. The correspondence between the eight-bit address,

an internal register address, and the defined machine state

is as follows:

Eight-Bit Internal Register
R Address Address Defined State 0000XXXX 0 - 15 Problem 0001XXXX 16 - 31 Supervisor and not any of the following 0010XXXX 32 - 47 SVC handler in problem state 0011XXXX 48 - 63 SVC handler in the supervisor state 0100XXXX 64 - 79 I/O handler in the problem state 0101XXXX 80 - 95 I/O handler in the supervisor state 0110XXXX 96 - 111 Invalid 0111XXXX 112 - 127 Invalid. 1000XXXX 128 - 143 Program interrupt handler

1

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in problem state 1001XXXX 144 - 159 Program interrupt handler in supervisor state

160 - 255 Invalid.
3. Registers may be passed between valid state pairs defined as

follows:

State Pair No. Applicable Passing State Pair 0 Problem & Supervisor

1 Problem & SVC handler

2 Problem & I/O handler

3 Problem & Program interrupt handler

4 Supervisor & SVC handler

5 Supervisor & I/O handler

6 Supervisor & Program inter...