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Address Generation for Multiple Program Level Control Store

IP.com Disclosure Number: IPCOM000086933D
Original Publication Date: 1976-Nov-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 104K

Publishing Venue

IBM

Related People

Bennett, TR: AUTHOR [+2]

Abstract

The control store address is incremented during control store access. The incrementer is a simple ripple incrementer with logic delays less than the control store access time. The incrementer output is latched in a program level address save register (CSAR SAVE) under program level control. Interrupt request lines are sampled to determine if a program level change will occur. The address in the selected program level address save register is gated to the control store address register selector (CSAR SAVE SELECTOR) for transfer into the control store address register (CSAR).

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Address Generation for Multiple Program Level Control Store

The control store address is incremented during control store access. The incrementer is a simple ripple incrementer with logic delays less than the control store access time. The incrementer output is latched in a program level address save register (CSAR SAVE) under program level control. Interrupt request lines are sampled to determine if a program level change will occur. The address in the selected program level address save register is gated to the control store address register selector (CSAR SAVE SELECTOR) for transfer into the control store address register (CSAR).

With reference to Figs. 1 and 2, the output of incrementer 25 must be valid at clock 9 time, thereby leaving clock 2 to 8 time for the incrementing function. Access of control store 10 starts at clock 2 time and extends to almost the end of clock 9 time. Control store 10 is addressed by CSAR 20 and the contents of the addressed location are transferred into instruction register (IR) 15 at clock 0 time.

The output CSAR 20 also feeds incrementer 25 and at the trailing edge of clock 9 time the incremented output is latched into either CSAR SAVE PL1 register 35 or CSAR SAVE PL2 register 45, depending upon which program level is active.

During clock 9 the interrupt request lines (not shown) were sampled to determine if a program level change will occur. The output of either register 35 or 45 is passed via CSAR SAVE SELECTOR 50 to CSAR SELE...