Browse Prior Art Database

Parity Predict for Incrementer Decrementer

IP.com Disclosure Number: IPCOM000086936D
Original Publication Date: 1976-Nov-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Beacom, TJ: AUTHOR [+3]

Abstract

A method is provided for designing parity-predict circuits for incrementers or decrementers with minimal logic. One operand for an incrementer or decrementer is always a known value. Only those operand bits which cause the final parity value to be the same as or different from the initial parity value are connected as inputs to the parity-predict circuit.

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Parity Predict for Incrementer Decrementer

A method is provided for designing parity-predict circuits for incrementers or decrementers with minimal logic. One operand for an incrementer or decrementer is always a known value. Only those operand bits which cause the final parity value to be the same as or different from the initial parity value are connected as inputs to the parity-predict circuit.

The first step is to generate a table setting forth the bits representing the initial value of data and associated parity bit and the incremented and decremented values and associated resultant parity bits. A table illustrating this step is set forth in Fig. 1. The next step is to determine which initial values, when incremented or decremented, will result in or not result in parity changes. This step is represented in Fig. 2. Those instances where the associated new parity bits differ from old parity bits are represented by an X.

From the tables it is seen that if bits b and c of the initial values are 01 for an increment or 10 for a decrement, the state of the new parity is the same as the original parity. In all other instances the state of the parity bit changes. Logic circuits for a three bit incrementer/decrementer (no change case) and a six bit incrementer/ decrementer (change case) designed according to this method are shown in Figs. 3 and 4 respectively. Depending upon the number of data bits being incremented or decremented, the parity-predict circuit is desig...