Browse Prior Art Database

Logic Arrays With Polysilicon Gate Lines

IP.com Disclosure Number: IPCOM000086963D
Original Publication Date: 1976-Nov-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 4 page(s) / 102K

Publishing Venue

IBM

Related People

Rideout, VL: AUTHOR

Abstract

Logic arrays with polysilicon gates generally utilize metal contacts to each gate. A method is disclosed that uses polysilicon gate lines (rather than metal lines) and yields a very dense array with simple processing.

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Logic Arrays With Polysilicon Gate Lines

Logic arrays with polysilicon gates generally utilize metal contacts to each gate. A method is disclosed that uses polysilicon gate lines (rather than metal lines) and yields a very dense array with simple processing.

Fig. 1 shows four potential field-effect transistor (FET) locations or "cells" of a programmable logic array (PLA) using self-registering metal to polysilicon gate contacts 1. [*] Two n+ output signal lines A and A can be connected to an nground line by activating either metal gate line B or B. The :AB FET location 2 is unoccupied (i.e., the FET is programmed out by omitting the channel region). Thus, the logic array is programmed at the first mask level.

The array shown in Fig. 1 is quite densely packed due to the utilization of self-registering gate contacts which allow smaller polysilicon gate areas than those associated with conventionally etched contact holes. A concern associated with this layout is that a reliable contact to each and every polysilicon gate must be made, and it is made directly over the active channel region of the FET.

One way to avoid directly contacting each polysilicon gate is to replace the n+ lines with metal lines, and replace the metal lines with polysilicon lines. The polysilicon gate lines are covered with an insulator such as silicon dioxide. The result of this approach is shown in Fig. 2. Here, the previously vertical n+ lines (A, A, and ground) are replaced by horizontal metal lines, and the previously horizontal metal lines (B and B) are replaced by vertical polysilicon gate lines. The metal lines now connect to nregions via conventional etched contact holes 3.

As shown in Fig. 2, a horizontal ground line services each pair of horizontal output lines A and A. An improvement in density can be achieved if one recognizes that the...