Browse Prior Art Database

AC Plasma Display Organization

IP.com Disclosure Number: IPCOM000086968D
Original Publication Date: 1976-Nov-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 5 page(s) / 113K

Publishing Venue

IBM

Related People

Schlig, ES: AUTHOR [+2]

Abstract

This is an arrangement for reducing the number of input connections to the decoder-driver circuitry of an AC plasma display and for simplifying the interconnection of such circuitry.

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AC Plasma Display Organization

This is an arrangement for reducing the number of input connections to the decoder-driver circuitry of an AC plasma display and for simplifying the interconnection of such circuitry.

Described are an organization technique and physical design for a plasma display panel having decoder-driver chips and interconnections mounted on the panel itself. The description primarily addresses the C-4 bonding of chips directly to metallization on the glass itself. It also discusses the possibility of using an intermediate flexible film chip carrier.

In order to achieve the projected economies in the plasma display panel, interconnections on the glass plates must be a single layer and should be producible by means of a minimal number of simple masks, preferably without lithography. This is achieved by organizing the display so as to minimize the number of interconnecting lines and by routing these lines beneath the chips and between C-4 connectors.

One existing gas panel driver module design uses 5 parallel bits to select one of the 32 output lines of a module and a 2-out-of-N code to select a module. In terms of 16-bit chips, directly attached to a hypothetical larger display organized in the conventional way, 4 output line selection bits and 8 chip selection bits (for 3-out-of-8 selection of 1 out of 40 chips) would be needed.

Adding the gate, set, reset, and 3 power supply lines, a total of 18 input lines would be distributed to all of the Y decoder-driver chips. Ten of these lines would connect to 10 contacts on each chip, while 8 would be rooted differently beneath each chip so that each chip would connect to a different set of 3 of the 8 lines. This is topologically possible, but certainly would adversely impact chip area and form factor, and also require complex mask design to route chip select lines differently at each chip.

It is proposed here that the number of input and power supply lines distributed to each chip be reduced to 8 by serially loading the output latches from a single input line and by selecting chips with a single pointer bit which is shifted from chip to chip. The latter is accomplished by placing a single shift register stage (designated the cursor register) on each chip and chaining together the inputs and outputs of stages on adjacent chips. A ninth wiring path may be used to chain chip cursor register outputs to chip cursor register inputs. A block diagram of the circuits on such a chip is shown in Fig. 1.

In accordance with Fig. 1, the states of the 16 driver switches DR (which determine which of the panel lines receive selection pulses and which receive only sustain pulses) are determined by the states of the corresponding stages of the serial-to-parallel shift register SR. This register is loaded by applying a 16-bit address string, serially in time, to the address data input line, connecting to all of the chips of the panel axis. Coincidentally, 16 shift pulses are applied to the ...