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Planar Triac Structures

IP.com Disclosure Number: IPCOM000086979D
Original Publication Date: 1976-Nov-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 5 page(s) / 139K

Publishing Venue

IBM

Related People

Feth, GC: AUTHOR [+2]

Abstract

This publication relates to the implementation of planar triac structures, and describes how this basic planar structure can be fabricated in a number of ways.

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Planar Triac Structures

This publication relates to the implementation of planar triac structures, and describes how this basic planar structure can be fabricated in a number of ways.

Triac devices are a well established device in industry and in the literature. However, as fabricated and described, they are made with vertical geometries extending through the semiconductor wafer (Fig. 1), and are not made with economical, planar semiconductor processes. The concept shows how the basic pnpn triac (or alternately an npnp) structure can be made in a basic planar configuration, shown here with two minor variations (Figs. 2 and 3). The basic structure is best seen in a cross section view, as in Fig. 4. As with the known vertical device structure of Fig. 1, when the triac is turned on by gating, signal currents conduct between electrodes 1 and 2 in either direction, subject to the applied electrode voltages. Referring to the planar layout (Fig. 2) the electrode metallization, since it must short the terminal p and n+ regions, provides connections to the required pnpn path for each current-carrying direction, although the paths are slightly different for each direction. A variation having extended n+ regions is shown in Fig. 3, and the design choice would be made on the basis of device requirements, such as series resistance, gate resistance, current and power densities, and gate sensitivities in various operating quadrants of gate current and main terminal current.

An improved structure is shown in Fig. 5. This structure has two basic differences from the previous structure: 1) a buried player which out-diffuses to join the upper p+ isolation diffusion, thereby reducing the isolation diffusion time and reducing the required epitaxy thickness and the device area; 2) an nsidewall diffusion joining the n+ buried layer, which then completely surrounds the active triac device and r...