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Polysilicon Gate MOSFETS for Weinberger Type Random Logic Arrays

IP.com Disclosure Number: IPCOM000086981D
Original Publication Date: 1976-Nov-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Cook, PW: AUTHOR [+4]

Abstract

The Weinberger random logic layout as described in reference [1] is a commonly used method in fabricating metal-oxide semiconductor field-effect transistor (MOSFET) chips with a single layer of metal. An example of a Weinberger array is shown in Fig. 1. The array uses diffused ground lines (sources) which may be electrically connected to diffused output lines (drains), by activating a metal input line connected to a metal or polysilicon gate. A difficulty with this approach is that DC currents must flow on diffused rails.

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Polysilicon Gate MOSFETS for Weinberger Type Random Logic Arrays

The Weinberger random logic layout as described in reference [1] is a commonly used method in fabricating metal-oxide semiconductor field-effect transistor (MOSFET) chips with a single layer of metal. An example of a Weinberger array is shown in Fig. 1. The array uses diffused ground lines (sources) which may be electrically connected to diffused output lines (drains), by activating a metal input line connected to a metal or polysilicon gate. A difficulty with this approach is that DC currents must flow on diffused rails.

As circuits are scaled down to smaller and smaller dimensions, it becomes increasingly difficult to maintain reasonable resistance in the ions. As the physical dimensions of the diffused lines becomes smaller, the resistance goes up. Thus the sheet resistance of the lines must be decreased, but this is prevented by the solubility limit of doping impurities.

Described is a technique for circumventing the sheet resistance problem in high-density Weinberger logic layouts. The technique is based on the polysilicon line approach which has been used commercially on the prior art for dynamic memories, but whose advantages for the case of Weinberger logic arrays has not been previously considered. The polysilicon line approach is, however, potentially most advantageous for use in random logic layouts, since the gate lines in the random logic arrays are only slightly populated (3 gates/line), while the programmed logi...