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Sequence Controller for Latching Logic

IP.com Disclosure Number: IPCOM000086982D
Original Publication Date: 1976-Nov-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Herrell, DJ: AUTHOR

Abstract

In a number of instances where latching logic is utilized, particularly with the use of inverters, it is necessary to generate a sequence of controlling pulses to determine the sequence of logical operations performed by a general combinatorial logic circuit. A number of circuits are shown whereby timing pulses can be generated and their start/stop time and/or width can be controlled by DC biases.

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Sequence Controller for Latching Logic

In a number of instances where latching logic is utilized, particularly with the use of inverters, it is necessary to generate a sequence of controlling pulses to determine the sequence of logical operations performed by a general combinatorial logic circuit. A number of circuits are shown whereby timing pulses can be generated and their start/stop time and/or width can be controlled by DC biases.

The basic timing circuit is shown in Fig. 1 wherein Josephson junctions J1 and J2 are latching Josephson junctions, switching either to the gap (2 Delta/e) or the same R(j). A control input, Ic1, to J1 initiates a pulse (i) through resistor R dy diverting current from J1 when it switches into the voltage state, and a control input, Ic2, to J2 terminates the timing pulse by switching J2 into the voltage state. A similar circuit is shown in Fig. 2, except that a portion 2 of the transmission line, through which current (i) flows, acts as a control line for device J2, providing a well defined pulse width which is determined by the control current threshold of J2 together with the pulse risetime and the propagation delay from J1 to J2. The addition of bias lines labeled "start" and "width" in Fig. 3 provide a variable start time/pulse width circuit, wherein the pulse is adjusted to have a well-defined exponential rise. Fig. 4 shows an arrangement in which the start and stop times can be triggered from the same edge of an input pulse by...