Browse Prior Art Database

Distributed Bubble Domain Storage System

IP.com Disclosure Number: IPCOM000086987D
Original Publication Date: 1976-Nov-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Lin, YS: AUTHOR [+3]

Abstract

This bubble domain memory allows imperfectly fabricated bubble chips and bubble memory chips damaged in operation to be salvaged by reconfiguring the system so that the undamaged parts will still be usable.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

Distributed Bubble Domain Storage System

This bubble domain memory allows imperfectly fabricated bubble chips and bubble memory chips damaged in operation to be salvaged by reconfiguring the system so that the undamaged parts will still be usable.

Fig. 1 depicts an example of the system organization of the proposed storage system. In this case the system consists of two major loops and m minor loops. The length of the major loops is m bits. Each minor loop comprises n mini-loops each of length m. A set of n+1 current conductors connect the mini-loops to the minor loops and couple the minor loops to the major loops. In normal operations, when the system is not in a read/write mode, none of the conductors is energized and, therefore, data cycle within each mini-loop. In the read/write mode, first conductor C(o) or C(n) is pulsed to transfer data to the desired major loop, then conductors C(1), C(2), ... C(n1) are pulsed synchronously to couple mini-loops to minor loops.

The proposed system could be implemented in conventional permalloy T-bar/I-bar devices. Fig. 2A illustrates the detailed overlay pattern around a junction between two adjacent mini-loops. Basically, the junction consists of a control line and two permalloy Y-bars. During normal operations, the control line is not energized. Bubbles in the mini-loops thus circulate independently around the two Y-bars following the in-plane field sequence marked 1, 2, 3, 4 (Fig. 2B). During the read/write operations, the control line is energized to connect the two mini-loops by transferring bubbles horizontally through the control gate (Fig. 2C).

To demonstrate the capability of testing and blocking out defective parts, assume a certain mini-loop has a defective bit position (defective T-bar, I-bar or disk), as marked by a cross in l(1n) (Fig. 1). A certain test bit pattern of length m is used to detect the location of the defect. Such a sequence of bits is first shifted from major loop M(1) into the minor loops, which at this point consist of the first column of mini-loops l(11), l(21), ..., l(m1) only. This is accomplished by pulsing conductor C(o) only. If this test is successful, the second column of mini- loops l(12), ..., l(m2) is connected to the first mini-loops to form the new minor loops. This is done by pulsing conductors C(o) and C(1). The same test sequence can be used, if repeated. This test procedure is repeated, each time allowing a new column of mini-loops to join the minor loops, until the defective position is located. The column which contains the defective mini-loop can then be blocked out by not pulsing the two conductors next to this column in read/write operations.

To demonstrate error isolation and recovery, consider two bit positions marked by triangles in Fig. 1. Due to physical imperfections, these positions tend to cause errors wit...