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Deductive Simulator

IP.com Disclosure Number: IPCOM000087001D
Original Publication Date: 1976-Nov-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 28K

Publishing Venue

IBM

Related People

Cha, CW: AUTHOR [+3]

Abstract

The deductive simulator method is an alternate to the parallel simulator method for the fault-simulation of binary digital logic circuits. In the deductive simulator a list of faults is generated to each gate that would change the signal output value of the gate. The active fault list must be accessible for all gates of the circuit. Assuming that there are n gates and that the number of faults is proportional to the number of gates, the size of this active fault list could be for the worst case, on the order of n/2/. This would make it unreasonable to keep this active fault list in core memory as soon as the gate count reaches a value of about 500 or more. While the typical simulation does not utilize all the space required by the active fault list, it still must exist for the worst case.

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Deductive Simulator

The deductive simulator method is an alternate to the parallel simulator method for the fault-simulation of binary digital logic circuits. In the deductive simulator a list of faults is generated to each gate that would change the signal output value of the gate. The active fault list must be accessible for all gates of the circuit. Assuming that there are n gates and that the number of faults is proportional to the number of gates, the size of this active fault list could be for the worst case, on the order of n/2/. This would make it unreasonable to keep this active fault list in core memory as soon as the gate count reaches a value of about 500 or more. While the typical simulation does not utilize all the space required by the active fault list, it still must exist for the worst case.

The typical solution to this problem is to allow the active fault list to reside on disk and keep sufficient buffers in core, so that almost always the active fault list is accessible in core. This introduces a certain overhead, reducing program efficiency and increasing program complexity. A method is described wherein the active fault list is allowed an amount of space which is at least some integer multiple of the gate count, and space is allowed for multiple simulation when excess space could possibly be required. Two cases for the present method are described. The first case is for combinational logic and the second case is for sequential logic.

For combinational logic the technique works basically as follows: Assume the length of the active fault list is l, and l = a + mn where n = number of gates m = the absolute value of l over n >/- 1

a = mod (l, m).

Also, the gates are ordered in a sequence such...