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Adaptive Analog to Digital Voltage Offset Cancellation

IP.com Disclosure Number: IPCOM000087002D
Original Publication Date: 1976-Nov-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 49K

Publishing Venue

IBM

Related People

Heller, LG: AUTHOR [+3]

Abstract

In a system such as the one shown in the figure, offset voltages can arise in the amplifier 10 and the voltage comparator 12. An important problem associated with precision analog-to-digital (A/D) converters is the presence of finite offset voltages. These offset voltages can have a magnitude several times that corresponding to the least significant bit of the converter, and thus pose a limit on the A/D converter accuracy. In conventional practice, this problem is alleviated by manual potentiometer adjustment calibration to cancel the undesirable offset voltages. However, the offset voltages of these devices are time dependent because they are subject to long-term drifts. Hence, in order to maintain converter accuracy, costly manual potentiometer adjustment calibration must be performed frequently.

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Adaptive Analog to Digital Voltage Offset Cancellation

In a system such as the one shown in the figure, offset voltages can arise in the amplifier 10 and the voltage comparator 12.

An important problem associated with precision analog-to-digital (A/D) converters is the presence of finite offset voltages. These offset voltages can have a magnitude several times that corresponding to the least significant bit of the converter, and thus pose a limit on the A/D converter accuracy. In conventional practice, this problem is alleviated by manual potentiometer adjustment calibration to cancel the undesirable offset voltages. However, the offset voltages of these devices are time dependent because they are subject to long-term drifts. Hence, in order to maintain converter accuracy, costly manual potentiometer adjustment calibration must be performed frequently.

Described below is an A/D offset voltage adjustment approach that utilizes a charge equalization technique. Automatic self-calibration is employed to eliminate the need of manual potentiometer adjustment calibration. This same adaptive operation can be done automatically by the system in the field to compensate for problems associated with long-term drifts, component aging and ambient temperature variations.

Since the silicon area required in this approach is small, the subsystem presented can be incorporated in a single large-scale integration (LSI) chip fabricated using conventional metal-oxide semiconductor (MOS) technology to achieve low cost.

An A/D converter which incorporates this adaptive offset cancellation feature is shown in the figure. It includes a weighted capacitor digital-to-analog converter (DAC) network, an amplifier, comparator, control logic and memory, and operates on the binary search principle.

The automatic offset cancellation portion 14 of the device contains a weighted capacitor network 16 connected in parallel to Vs via switches, some control logic 18 and a small memory register 20. The control logic, working in conjunction with the comparator determines and identifies a combination of switch operations to achieve the correct offset voltage cancellation by means of charge equalization. The register "remembers" this combination of switches to create the same charge equalization to achieve offset cancellation every time an A/D operation is performed. The granularity of the weighted capacitors in the network is chosen to meet the offset cancellation error which can be tolerated. The voltage offset cancellation can be done automatically in the following manner:

The weighted capacitor network portion 14 is designed such that the sum of all the weighted capacitors in the network equals Delta, i.e.,

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Delta is chosen such that Delta over 2C V(s) >/- the absolute value of V(osm) where Vs is the referen...