Browse Prior Art Database

Storage Mapping

IP.com Disclosure Number: IPCOM000087022D
Original Publication Date: 1976-Dec-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Monroe, JR: AUTHOR

Abstract

A technique is described for facilitating the tracing of storage maps by blocking parity checking and generating while inverting the parity bit associated with each instruction as it is executed or referenced in storage. Accordingly, a storage dump printout at any point in the execution of the program will permit easy tracing of the instructions actually executed by keying on the bad parity bits. That is, the parity bit is effectively utilized as a flag bit for the executed instructions. The technique is inexpensive and useful with any applicable programming. A representative system would include a central processing unit (CPU) and, at least, a system printer for output.

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Storage Mapping

A technique is described for facilitating the tracing of storage maps by blocking parity checking and generating while inverting the parity bit associated with each instruction as it is executed or referenced in storage. Accordingly, a storage dump printout at any point in the execution of the program will permit easy tracing of the instructions actually executed by keying on the bad parity bits. That is, the parity bit is effectively utilized as a flag bit for the executed instructions. The technique is inexpensive and useful with any applicable programming. A representative system would include a central processing unit (CPU) and, at least, a system printer for output.

Previously, storage mapping/program tracing has been accomplished by two basic methods:
1. By introducing additional code to an already existing module

to allow tracing of the logic.
2. By hooking external hardware to monitor the instruction

address register, with some method of off-line storage. The above methods work but with limitations. Additional code alters the execution rate of the programming under consideration. External hardware is expensive and results in a data reduction problem.

While flag bits have been used for designating storage locations that have been referenced, such as in dynamic address translation, and the general concept of disabling parity checking and generating has been used in other testing operations, the present arrangement differs by making use of pa...