Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Pulse Former

IP.com Disclosure Number: IPCOM000087050D
Original Publication Date: 1976-Dec-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Dunn, EC: AUTHOR [+2]

Abstract

An asynchronous input control signal needs to be synchronized to a set of system clocks, C1 and C2, for controlling a device (not shown) which has a plurality of synchronizable states 1 thru 4. A single pulse is created while synchronizing the leading edge of the asynchronous input. The rise of a reference gate for controlling a synchronous device occurs at the fall of the single pulse and the fall of the gate is synchronized to the trailing edge of the asynchronous input. The resynchronizing circuits use a so-called two-level shift register latch consisting of L1 and L2. Clock C2 latches data into the first level L1 while clock C1 shifts the L1 data into the second level latch L2. Latches relating to the leading edge are termed L1L and L2L and to the trailing edge are referred to as L1T and L2T.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 77% of the total text.

Page 1 of 2

Pulse Former

An asynchronous input control signal needs to be synchronized to a set of system clocks, C1 and C2, for controlling a device (not shown) which has a plurality of synchronizable states 1 thru 4. A single pulse is created while synchronizing the leading edge of the asynchronous input. The rise of a reference gate for controlling a synchronous device occurs at the fall of the single pulse and the fall of the gate is synchronized to the trailing edge of the asynchronous input. The resynchronizing circuits use a so-called two-level shift register latch consisting of L1 and L2. Clock C2 latches data into the first level L1 while clock C1 shifts the L1 data into the second level latch L2. Latches relating to the leading edge are termed L1L and L2L and to the trailing edge are referred to as L1T and L2T. The illustrated circuits remove uncertainties arising from synchronizing both the rise and fall of an asynchronous control signal.

Immediately after the rise of the asynchronous input, which can vary in times indicated by the dotted line on the input signal, latch L1L is activated by C2 to supply out-1. Out-1 provides a single controlling pulse to the device. At the first C1 following the C2 time setting L1L, the set condition of L1L is transferred to L2L. The active state of L2L resets L1L at the next C2 and prevents L1L from being again set to active condition until L2L itself is reset. On the next occurring C2 signal, latch L2T is set, which provides out-...