Browse Prior Art Database

Double Level Polysilicon Memory Cell Process

IP.com Disclosure Number: IPCOM000087058D
Original Publication Date: 1976-Dec-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Adler, E: AUTHOR [+2]

Abstract

U. S. Patent 3,841,926 describes a process for fabricating a single device memory cell which includes an aluminum gate field-effect transistor (FET) and polysilicon field shield-to-diffusion storage capacitor. Thin dielectric for the channel region of the FET, as well as for the storage capacitor, comprises a silicon nitride passivated thermal oxide layer. The presence of the dual dielectric structure in the gate oxide tends to cause device instabilities because of charge trapping centers present in the two-layer dielectric structure. This process provides a silicon gate FET having a silicon dioxide dielectric while retaining most of the benefits of aluminum metallurgy. The process description includes alternative gate dielectric processes and alternative metal etching techniques.

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Double Level Polysilicon Memory Cell Process

U. S. Patent 3,841,926 describes a process for fabricating a single device memory cell which includes an aluminum gate field-effect transistor (FET) and polysilicon field shield-to-diffusion storage capacitor. Thin dielectric for the channel region of the FET, as well as for the storage capacitor, comprises a silicon nitride passivated thermal oxide layer. The presence of the dual dielectric structure in the gate oxide tends to cause device instabilities because of charge trapping centers present in the two-layer dielectric structure. This process provides a silicon gate FET having a silicon dioxide dielectric while retaining most of the benefits of aluminum metallurgy. The process description includes alternative gate dielectric processes and alternative metal etching techniques.

1. Process semiconductors, as described in U. S. Patent 3,841,926 through polysilicon field shield oxidation. This includes doped oxide diffusion, thin thermal oxide, thin silicon nitride deposition, blanket polysilicon field shield, etching of field shield to selectively exposed nitride and thermal oxidation of polysilicon. Exposed nitride will prevent further oxidation in FET gate areas.

2a. Remove exposed nitride from part of or all of wafer with hot phosphoric acid or by photomasked ion etching. Clean wafer and thermally grow, or deposit by chemical vapor deposition, additional silicon dioxide to provide desired gate dielectric thickness....