Browse Prior Art Database

Dynamically Variable Error Action

IP.com Disclosure Number: IPCOM000087065D
Original Publication Date: 1976-Dec-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Callahan, RW: AUTHOR

Abstract

A microprogrammed processing system for providing I/O channeling support to a host data processing system may refer to hierarchical host storage for its program instructions and microinstructions. In order to achieve rapid recovery from transient system errors, each execution by the support processing system of a microinstruction, which involves reference to pages stored in the host system, may be "safeguarded" by a branch-on-error "follow-on" action (i. e., a conditional branch microinstruction taken after each storage reference). However, this makes for unwieldy "overhead" writing and execution of ancillary branch microinstructions. and may be completely ineffective relative to a storage reference, which may overlay and effectively erase the microinstruction calling for the reference.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 71% of the total text.

Page 1 of 1

Dynamically Variable Error Action

A microprogrammed processing system for providing I/O channeling support to a host data processing system may refer to hierarchical host storage for its program instructions and microinstructions. In order to achieve rapid recovery from transient system errors, each execution by the support processing system of a microinstruction, which involves reference to pages stored in the host system, may be "safeguarded" by a branch-on-error "follow-on" action (i. e., a conditional branch microinstruction taken after each storage reference). However, this makes for unwieldy "overhead" writing and execution of ancillary branch microinstructions. and may be completely ineffective relative to a storage reference, which may overlay and effectively erase the microinstruction calling for the reference.

This can be avoided if a nonvolatile instruction (or microinstruction), named "Load Routine Address" (LRA), is used by the system to accomplish anticipatory loading of a backup register with an origin address, specified in the instruction, linking to a selective microroutine for recovery action. Upon occurrence of storage error, nonvolatile (hardware) controls of the system operate to transfer the contents of the backup register into the instruction counter governing system sequencing, thereby activating a recovery sequence appropriate to the immediate state of the system.

Consider, for instance, a system sequence for retrieving a Unit Control Wor...