Browse Prior Art Database

Fabrication of I/2/L Circuits

IP.com Disclosure Number: IPCOM000087080D
Original Publication Date: 1976-Dec-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 46K

Publishing Venue

IBM

Related People

Anantha, NG: AUTHOR [+2]

Abstract

This is a process for fabricating integrated injection logic (I/2/L) circuits that provides significant improvements over prior techniques in the two main electrical characteristics of the inverse NPN and the lateral PNP transistors constituting I/2/L circuits. The two main electrical characteristics are the current gain, Beta, and the gain-bandwidth frequency, f(tau). Improvements in Beta and f(tau) of the transistors result in reduction of the logic circuit delay at any particular power level in the conventional power range of operation of I/2/L circuits.

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Fabrication of I/2/L Circuits

This is a process for fabricating integrated injection logic (I/2/L) circuits that provides significant improvements over prior techniques in the two main electrical characteristics of the inverse NPN and the lateral PNP transistors constituting I/2/L circuits. The two main electrical characteristics are the current gain, Beta, and the gain-bandwidth frequency, f(tau). Improvements in Beta and f(tau) of the transistors result in reduction of the logic circuit delay at any particular power level in the conventional power range of operation of I/2/L circuits.

The process, described sequentially, is as follows:

1. Starting with an N+ type silicon wafer 2 having resistivity in the range of
0.01-0.001 ohm-cm, grow in the wafer about 10 mu m thick N- type epitaxial silicon 4 of 0.1-0.5 ohm-cm resistivity.

2. Grow about 10K Angstrom thick thermal silicon dioxide 6 at the surface of the epitaxial silicon layer.

3. Using a conventional photolithographic technique involving a photoresist and an appropriate mask, etch windows in the silicon dioxide 6.

4. Obtain, in an epitaxy reactor, 12-16 mils thick layer of N+ type silicon 8 on top of the wafer. The portion of the silicon layer 8 over silicon 4, which was bare at the windows in the silicon dioxide 6, will be monocrystalline. The portion of the silicon layer 8 above the remnant silicon dioxide 6 will be polycrystalline.

5. Through electrochemical etching, etch away the original N+ region 2.

6. Through chemical etching, etch away 8-9 mu m thick layer from the N- region 4 leaving 1-2 mu m layer on the substrate. The wafer is flipped upside down at this stage and all subsequent processing is done at the "...