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High Density Serial Parallel Serial CCD Memory

IP.com Disclosure Number: IPCOM000087082D
Original Publication Date: 1976-Dec-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Cases, M: AUTHOR [+3]

Abstract

Fig. 1 shows a layout that permits the bit width of a parallel register to be independent of the bit length of a serial register. The bit width of the parallel register can, thereby, be maintained at minimum within the layout ground-rule limitations.

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High Density Serial Parallel Serial CCD Memory

Fig. 1 shows a layout that permits the bit width of a parallel register to be independent of the bit length of a serial register. The bit width of the parallel register can, thereby, be maintained at minimum within the layout ground-rule limitations.

To obtain a maximum bit density, the parallel registers are designed with minimum channel separation. The serial registers are then designed such that the projected bit length of the serial register of Fig. 1 is identical to the bit width of the parallel register. The transfer channel width and corresponding spacing is assumed to be less than the bit width of the parallel register.

The operational principle can be described as follows (assuming a p-type substrate and an n-type transfer channel): When the data is read into the serial register, the transfer gate is maintained at a low potential. Hence, the transfer channel is isolated from the input register. Meanwhile the transfer channel potential is maintained at V(max), as indicated in Fig. 2A. As the serial register is filled with information, the potential of the transfer gate is raised, allowing for charge transferring from the serial to the parallel register through the transfer channel, as indicated in Fig. 2B. After the transfer is completed, the transfer gate resumes its blocking state and charge begins to flow through the parallel registers.

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