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Driver Latch Circuit

IP.com Disclosure Number: IPCOM000087088D
Original Publication Date: 1976-Dec-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Eardley, DB: AUTHOR

Abstract

Memory drivers may generate false output signals ("glitches" and "popdowns") under certain conditions. The external driver latch circuit shown in the figure solves these problems. The circuit comprises basically a differential amplifier T2-T3 having an output to an active pullup T4, TAP, T5 and a feedback from the output to the base of T3.

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Driver Latch Circuit

Memory drivers may generate false output signals ("glitches" and "popdowns") under certain conditions. The external driver latch circuit shown in the figure solves these problems. The circuit comprises basically a differential amplifier T2-T3 having an output to an active pullup T4, TAP, T5 and a feedback from the output to the base of T3.

"Popdown" is characterized by low-voltage outputs in the illustrated latch circuit and clock circuit (not shown) at high temperatures. To eliminate the popdown in the latch circuit, resistor R7, which appears in the chip, is shorted in order to lower the down-level voltage at the collectors of T2 and T3. This reduces the number of up-level failures at the output which are caused by marginal up-level voltages.

To eliminate the popdown in the clock circuit (not shown), the leading and trailing edges of the CLOCK pulse are delayed behind the corresponding edges of the CLOCK pulse. This is accomplished simply by inverting the CLOCK output pulse to generate the CLOCK pulse.

This solution makes it necessary to change the latch circuit configuration. The leading edge delay of the clock pulse results in the delay of the rise of potential V3, which is further delayed by the RC time constant at the input of the latch circuit. This delay results in an interval t, when both transistors T2 and T3 are turned off. Assuming that both the array data input signal and the circuit output signal V(OUT) of the latch are initiall...