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Browse Prior Art Database

Substrate Compensation for Depletion Mode FET Circuits

IP.com Disclosure Number: IPCOM000087089D
Original Publication Date: 1976-Dec-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Blaser, EM: AUTHOR [+2]

Abstract

This is a substrate voltage detector for an on-chip substrate voltage generator, particularly for field effect transistor (FET) circuits utilizing depletion mode technology.

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Substrate Compensation for Depletion Mode FET Circuits

This is a substrate voltage detector for an on-chip substrate voltage generator, particularly for field effect transistor (FET) circuits utilizing depletion mode technology.

On-chip substrate voltage generators are well known in the art and, typically, utilize a controlled oscillator output for drawing a desired amount of current from the substrate, thereby causing the substrate to have a potential level more negative than the most negative supply potential. It is desirable to precisely control the substrate bias voltage. Circuits for detecting substrate bias voltage and for providing an output suitable for controlling the oscillator output are known for enhancement mode FET circuits. Such a circuit suitable for use in depletion- mode FET technology is illustrated in the drawing.

As shown, depletion-mode devices T1 and T2 form a voltage divider which generates a reference voltage at node N2. This reference voltage may be set at two volts, for example, and supplied to a detector transistor, which is depletion- mode device T3. When the threshold of T3 is low (e.g., -2.5 volts), device T3 will be turned on by the 2 volt reference potential. This will cause node N5, also, to be brought to 2 volts. The potential at node N5 is amplified with the proper phase by the two inverter stages including transistors T5, T6, T7 and T8. The substrate bias voltage generating circuit receives the output from the output node brin...