Browse Prior Art Database

MTL Set Reset Latch Circuit

IP.com Disclosure Number: IPCOM000087095D
Original Publication Date: 1976-Dec-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 5 page(s) / 198K

Publishing Venue

IBM

Related People

Robbins, GJ: AUTHOR

Abstract

The disclosed latching structure is: (1) fully compatible with merged transistor logic (MTL); (2) more compact than basic MTL logic element implementations; (3) offers logically independent clock inputs allowing simpler clock-powering structures than with basic MTL latches; (4) is logically hazard-free; (5) can support multiple clocked data ports; and (6) offers increased performance over conventional MTL implementations by virtue of current switch action and bootstrapping of data outputs.

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MTL Set Reset Latch Circuit

The disclosed latching structure is: (1) fully compatible with merged transistor logic (MTL); (2) more compact than basic MTL logic element implementations; (3) offers logically independent clock inputs allowing simpler clock-powering structures than with basic MTL latches; (4) is logically hazard- free; (5) can support multiple clocked data ports; and (6) offers increased performance over conventional MTL implementations by virtue of current switch action and bootstrapping of data outputs.

Fig. 1 shows the basic set/reset latch circuit. Fig. 4 shows a sample lay-out of the circuit in its simplest embodiment. The circuit consists of two isolated collector diffusions containing isolated base regions separated by recessed oxide isolation (ROI). Each of the isolated collector diffusions has base and emitter(s) contacts. A third isolated collector diffusion, common to the structure containing multiple latching elements, contains isolated lateral PNP current source devices.

The first isolated collector structure mentioned above contains devices 7, 8, 9 and 10, which are inverse-region operated NPN transistor structures, and device 15, which is a normally operated NPN structure. Similarly, the second isolated collector diffusion structure contains devices 11, 12, 13 and 14 as inverse NPN's and device 16 as a normal NPN. Devices 8 and 13 serve as clock gating elements for the latch circuit. They require a pullup element if the circuit driving them does not provide one (e.g., MTL logic circuit). This pullup element may be a pullup resistor or an independent lateral PNP, as depicted by devices 2 and 5 in Fig. 1.

A single lateral PNP pullu...