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Array Logic Short Path

IP.com Disclosure Number: IPCOM000087096D
Original Publication Date: 1976-Dec-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Related People

Robbins, GJ: AUTHOR

Abstract

The general structure of a programmable logic array (PLA) is shown in Fig. 1. Logical data is presented to the PLA inputs, after which it is decoded via single- or double-bit partitioning. Then it is presented to the AND array where it is utilized, as per the associative array concept, to perform a parallel interrogation of all words (called product terms) in the array and to filter out those which fit the logical "match" between input data and individual word personalization. In performing this operation, a large amount of logical "power" is experienced.

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Array Logic Short Path

The general structure of a programmable logic array (PLA) is shown in Fig.
1. Logical data is presented to the PLA inputs, after which it is decoded via single- or double-bit partitioning. Then it is presented to the AND array where it is utilized, as per the associative array concept, to perform a parallel interrogation of all words (called product terms) in the array and to filter out those which fit the logical "match" between input data and individual word personalization. In performing this operation, a large amount of logical "power" is experienced.

The matched AND array product terms then drive their respective OR array product term words, and in doing so gain additional logical function since matched product terms may be OR'ed together on the OR array bit lines.

The output data from the OR array bit lines is presented to a latching structure where additional logical function may be experienced due to logical operations performed in this structure. From the output of the latches, the data is driven off-chip by conventional driving mechanisms.

Described below is a new associative array organization which can provide a fast path through a master-slice PLA structure. This fast path is significant because the system logic designer finds many situations where logical power of the PLA cannot be utilized due to the cycle time of the PLA being greater than acceptable for controlling critical functions. In many instances, for example, the PLA cycle time becomes the machine cycle time, since the PLA could be the slowest delay element in the system. In this case, if an event external to the PLA is meant to be controlled in one cycle, given valid data for control, then this logic must be performed external to the...