Browse Prior Art Database

Clock Pulse Number Monitor

IP.com Disclosure Number: IPCOM000087097D
Original Publication Date: 1976-Dec-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Bello, SE: AUTHOR [+2]

Abstract

Computer clock pulse generators controlled by an input control field of an instruction word produce a number of clock pulses specified by the field. To check performance, the clock pulses actually generated are counted and compared to the count specified by the input control field. Where the clock pulse generator is controlled to provide a variable even number or variable odd number of pulses, performance is checked with the use of a resettable toggle flip-flop without counting the clock pulses actually generated.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 76% of the total text.

Page 1 of 2

Clock Pulse Number Monitor

Computer clock pulse generators controlled by an input control field of an instruction word produce a number of clock pulses specified by the field. To check performance, the clock pulses actually generated are counted and compared to the count specified by the input control field. Where the clock pulse generator is controlled to provide a variable even number or variable odd number of pulses, performance is checked with the use of a resettable toggle flip-flop without counting the clock pulses actually generated.

Referring to the figure, the input control field applied to terminal 1 is decoded
(2) to control clock generating network 3 to produce a number of clock pulses on output lines 4, as designated by the control field. The input at 1 is also decoded
(5) into a signal representing the expected (desired) number of clock pulses. The actual clock pulses are counted (6), and the actual count value and the expected count value are compared (7) to provide an error output (8) if the compared counts are not the same.

In cases where the clock generating network 3 is controlled to produce an even or an odd predetermined count of nonoverlapping clock pulses, performance may be monitored by ORing the actual clock pulses on lines 4 in circuit 9 and applying the result to the toggle input of flip-flop 10. Elements 5, 6 and 7 are not used in this instance. Flip-flop 10 is reset (input R) prior to the initiation of the clock pulses from network 3....