Browse Prior Art Database

Dynamic Detection and Monitoring of State Change Information in Microprocessor Engines

IP.com Disclosure Number: IPCOM000087101D
Original Publication Date: 1976-Dec-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Galli, EJ: AUTHOR [+5]

Abstract

A mechanism is provided in a microprocessor engine to allow all significant changes of state occurring in the engine to be recorded and monitored while these changes are occurring dynamically in either normal or abnormal modes of operation. The engine state change data are transferred with speed and simplicity to a monitor/test adapter connected to the engine via an input/output (I/O) interface.

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Dynamic Detection and Monitoring of State Change Information in Microprocessor Engines

A mechanism is provided in a microprocessor engine to allow all significant changes of state occurring in the engine to be recorded and monitored while these changes are occurring dynamically in either normal or abnormal modes of operation. The engine state change data are transferred with speed and simplicity to a monitor/test adapter connected to the engine via an input/output (I/O) interface.

In the typical configuration shown, microprocessor engine 1 is connected to memory 2 and to one or more I/O adapters (not shown). Monitor/test adapter 3 is attached via the I/O interface 4 and, optionally, via the memory/external memory address (EMA) interface 5. The engine, in addition to its basic functions, contains additional special state-change detection and transfer logic functions. Associated with this mechanism are two special external interface lines 6 and 7, labeled special monitor sequence and monitor data, respectively, which connect the engine to the monitor adapter. The scan lines 8 are used for register scans. The additional control lines 9 include the standard set of external/test lines. These include "single instruction", "single cycle", "single clock" and "start" lines, as well as clock lines, special test lines, etc.

All significant changes of state (i.e., changes to contents of control/status registers, operational state changes, mode changes, etc.) in the microprocessor engine may be grouped into two categories:
(1) those caused by the execution of control instructions, and
(2) those which occur automatically, internally in the engine

(e.g., as a result of machine check/program check condition,

engine entering the "wait" state, etc.), including

state-changes resulting from interrupts of various types

causing program status word swaps.

The monitor condition state-change recognition

logic 10 detects each of these types of

state-changes and sets up one of two types of control and

transfer sequences, a control instruction sequence or a

special monitor sequence. There is a very slight speed

penalty for the first, and no penalty for the se...