Browse Prior Art Database

Shared Facility Supervisor

IP.com Disclosure Number: IPCOM000087103D
Original Publication Date: 1976-Dec-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 56K

Publishing Venue

IBM

Related People

Antanaitis, BC: AUTHOR [+3]

Abstract

The sharing of facilities such as, for example, storage registers by two asynchronous contending users such as data processors, requires a supervisor to ensure that the shared facility and the engaged first user are protected from interference from the contending second user. The supervisor grants or denies use of the register space by responding to each request in such a manner that the requester can determine its subsequent action.

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Shared Facility Supervisor

The sharing of facilities such as, for example, storage registers by two asynchronous contending users such as data processors, requires a supervisor to ensure that the shared facility and the engaged first user are protected from interference from the contending second user. The supervisor grants or denies use of the register space by responding to each request in such a manner that the requester can determine its subsequent action.

Referring to the figure, the two asynchronous contending users are microprocessor 25 and computer system channel 26. If channel 26 delivers a channel-initiated selection sequence of signals (tags) via line 1, channel condition decode 19 produces a signal on line 14 which conditions AND gate 27 toward conduction. After the termination of the signal on line 14, decode 19 provides a signal on line 2 which sets "busy" latch 24. At the same time, gate 21 passes an initiating signal from decode 19 on line 28 to shared facilities control
22. Thus, the channel has gained access to shared facilities 29 and completes its operation.

Until the microprocessor completes its part of the interactive operation originally started by the channel, the busy latch remains set. If, during this time the channel again attempts to use the shared facilities, decode 19 produces a second signal on line 14. This time AND gate 27 conducts because busy latch 24 still is set. Temporary busy generator 20 is activated and a short busy sequence is sent back to channel 26 via line 6. Simultaneously, the output from AND gate 27 on line 11 inhibits gate 21 preventing operation of shared facilities control 22 in response to any channel request. Latch 24 is reset when a bit on line 8 from microprocessor 25 in combination with appropriate tags on line 3 inform microprocessor condition deco...