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Improving Switching Speed of MTL I/2/L Circuitry

IP.com Disclosure Number: IPCOM000087113D
Original Publication Date: 1976-Dec-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 45K

Publishing Venue

IBM

Related People

Berger, HH: AUTHOR [+2]

Abstract

Merged transistor logic (MTL), also known as integrated injection logic (I/2/L), is an advanced bipolar large-scale integration (LSI) concept discussed, for example, in Electronics, September 4, 1975, pp. 89-94 and October 2, 1975, pp. 99-103.

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Improving Switching Speed of MTL I/2/L Circuitry

Merged transistor logic (MTL), also known as integrated injection logic (I/2/L), is an advanced bipolar large-scale integration (LSI) concept discussed, for example, in Electronics, September 4, 1975, pp. 89-94 and October 2, 1975, pp. 99-103.

An area in MTL requiring improvement is the relatively low intrinsic switching speed compared with other bipolar logic circuits, such as ECL and TTL. The main reasons for this are the low intrinsic switching speed of the inversely operated npn transistor structure and the increased carrier storage resulting from the high saturation of the switched-on npn transistors.

The intrinsic switching speed of the inverse npn transistor can be improved be reducing as far as possible the parasitic currents flowing outside the intrinsic transistor by suitable geometry and a suitable doping profile. Generally, however, such measures increase considerably the current gain of the inverse transistor structure, which, in case of saturation, negatively affects the carrier storage.

As the inverse current gain of the inverse npn structure is very high (corresponding to the normal current gain of the normal npn structure), the carrier storage of the saturated inverse npn structure is proportional to the current gain Beta of this inverse npn structure. Carrier storage Q(B) is
Q(B) approx. I(B) . Beta . Zeta(E). where the emitter time constant Zeta(E) = 1 over 2 Pi f(T) (f(T) = transit frequency). Thus,by improving the intrinsic switching speed. carrier storage Q(B), governing the switching speed, is not reduced to the required extent because of the higher current gain.

It is reommended that the effective current gain Beta = I(C1)/I(1) of the inverse npn structure be reduced by means of a parallel diode D (Fig. 1). For this purpose the current/voltage characteristic of this speed-up diode must be so adapted to the base/emitter diode characteristic that the required effective current gain Beta is obtained. To I(B) << I(1) the following applies: Beta approx. C1 over I(D) approx. I(E) over I(D) where the diode time constant Zeta(D) is Zeta(D) < or Approximately = Zeta(E). since, otherwise, the switching speed deteriorates too much as a result of the carrier storage of this diode.

Fig. 2 shows plan and sectional views of a typical layout, whereby parallel diode D, for eliminating the excess current gain, is realized by a further parallel MTL-collector in the form of an additional n+ region 1 short-circuited to base contact 2. The characteristics of the transistor structure, connected as a diode and comprising zones 3-4-1, differ substantially from those of the extrinsic base- emitter diode, with zones 4-3 and base contact 2, present in conventional MTL structures. The current density ratio is about 50; in addition, the carrier storage is considerably less. Depending upon the Beta(ef...