Browse Prior Art Database

N+ Multiple Underpass Device

IP.com Disclosure Number: IPCOM000087127D
Original Publication Date: 1976-Dec-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Price, CA: AUTHOR [+2]

Abstract

Known low-impedance crossover devices in N type epitaxial integrated circuit chips use a P type isolation diffusion 11 to create islands 13, each containing one low resistance N+ underpass diffusion 17, as in Fig. 3. Such single-device islands require substantial chip area.

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N+ Multiple Underpass Device

Known low-impedance crossover devices in N type epitaxial integrated circuit chips use a P type isolation diffusion 11 to create islands 13, each containing one low resistance N+ underpass diffusion 17, as in Fig. 3. Such single-device islands require substantial chip area.

If voltages are low and some capacitance can be tolerated, multiple N+ underpasses can be placed in the same island 13 by providing a diffused P type bed 15 within the island 13 for isolation between N+ underpasses 17, as in Fig. 1. Metallization 19 connects bed 15, island 13, and isolation diffusion 11 to the most negative voltage on the chip which might be zero volts.

The advantage of multiple underpasses in a single isolation island are most apparent in bus routing on a chip, as shown in Fig. 2. The lower voltage breakdown threshold and higher capacitance of a multiple underpass arise from vertical NPN parasitic devices comprising regions 13, 15 and 17 and horizontal PNP parasitic devices comprising regions 15, 13 and 11. Metallization 19 keeps these parasitic devices turned off but some degradation in breakdown voltage and increase in capacitance occurs nonetheless.

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