Browse Prior Art Database

PLA Implementation of a PLO

IP.com Disclosure Number: IPCOM000087128D
Original Publication Date: 1976-Dec-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 40K

Publishing Venue

IBM

Related People

Grice, DG: AUTHOR

Abstract

Programmable logic array (PLA) technology takes advantage of the cost reductions possible with large-scale integration, but without the usual high circuit development cost because a PLA can be personalized during a last metallization process step. Although usually considered to be a digital control logic implementation method, PLAs can also be applied to digital communication circuits such as a phase locked oscillator (PLO), as shown in Fig. 1.

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PLA Implementation of a PLO

Programmable logic array (PLA) technology takes advantage of the cost reductions possible with large-scale integration, but without the usual high circuit development cost because a PLA can be personalized during a last metallization process step. Although usually considered to be a digital control logic implementation method, PLAs can also be applied to digital communication circuits such as a phase locked oscillator (PLO), as shown in Fig. 1.

Fig. 1 at page 111 of an article by J. C. Logue et al, in the March 1975 IBM journal of Research and Development shows the hardware functional block diagram of a PLA and tables 1 and 2 at page 113 show the logical meaning of the symbols used in the personality table below which is the PLA implementation of the circuit of Fig. 1.

As shown therein, the following symbols and functions are related: UU = A and B unequal, NN = not A or not B, PP =

A or B, I = A, O = not A, . = don't care, S = set Flip Flop, R = reset Flip Flop, and T = change state or toggle Flip Flop, where A and B are input variables.

Referring to Figs. 1 and 2 above, new data to be clocked is compared in exclusive OR 23 with old data from delay 21 to detect data transitions. Compare gates 25 compare each data transition with the state of counter 27 to toggle flip- flop circuit 29. Counter 27 operates at a modulus of 16 under control of product term 17 if the data transition occurs at the negative clock transition, e.g., at a count of 15 or 0, as shown in Fig. 2. The counter stages are shown for a count modulus of 16 in Fig. 2. If the data changes when clock toggle 29 is on and counter 27 is at a count of 8 through 14, the clock is late and must be speeded up by changing the modulus of counter 27 to 15 which is accomplished at product terms 2 or 3 and 18. If the data changes when clock toggle 29 is off and counter 27 is at a count of 1 through 7, the clock is early and must be reduced in frequency by changing the modulus of mounter 27 to 17 at produ...