Browse Prior Art Database

Data Security Device

IP.com Disclosure Number: IPCOM000087133D
Original Publication Date: 1976-Dec-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Prentice, PN: AUTHOR

Abstract

Doubling the data rate of a data security device is achieved by allowing two operands, offset by a predetermined time period, to be processed concurrently.

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Data Security Device

Doubling the data rate of a data security device is achieved by allowing two operands, offset by a predetermined time period, to be processed concurrently.

Fig. 1 illustrates a simplified block diagram of a block cryptographic device of the type described in U. S. Patent 3,958,081, with the 4-clock-phase timing of the field-effect transistor (FET) chip indicated in the logical blocks. Each clock phase is 250 nanoseconds in duration, thereby providing a one microsecond clock cycle. It can be seen that the device has two levels of storage in the loop, which consists of the upper data register, first set of exclusive OR circuits, substitution boxes and a second set of exclusive OR circuits connected to the upper data register, with the two levels being offset by four phase times. Therefore, it is possible to have two blocks of data in the loop at the same time that are offset by four phase times, thereby doubling the data rate. This can be accomplished by inverters (shown in dotted block form) at indicated points in the data security device. Assuming a 16-round cipher process and a continuous stream of data input, two blocks of data will always be in the loop eight rounds and four phase times apart.

Normal encipherment operation of the data security device starts by loading a data block into the input buffers and then into the data registers. In the first round, the upper half of the data block consisting of 32 data bits is expanded to 48 bits and combined by the first set of exclusive OR circuits with 48 cipher key bits selected from the 56 cipher key bits, in accordance with an arbitrary but fixed permutation. The 48-bit output of the first set of exclusive OR circuits is then applied to the substitution boxes to perform a transformation function yielding a substitution set of 32 bits which may further be permuted by a linear transformation to produce a 32-bit product block cipher of the first half of the data block. The 32-bit second half of the data block is then modified by the 32-bit product block cipher of the first half of the data block in the second set of exclusive OR circuits and fed back along the loop to replace the contents of the upper data register, namely, the first half of the data block. At the same time, the contents of the upper data register are transferred to the lower data register to complete the first round. The cipher key is then shifted in accordance with a predetermined shift schedule to provide a new set of cipher key bits.

In the second round, the 32-bit modified second half of the data block is combined with the new set of cipher...