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Depletion Mode FET Load Devices Switched with Positive Signal Voltage Levels

IP.com Disclosure Number: IPCOM000087135D
Original Publication Date: 1976-Dec-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Delahanty, RJ: AUTHOR [+3]

Abstract

This driver circuit has a low capacitance input impedance and fast switching speed without increased power consumption. The basic switching circuit includes enhancement-mode output field-effect transistors (FETs) 11 and 13 and inverting FETs 15 and 17. The inverting FETs 15 and 17 isolate the input from the large gate capacitance of the output transistors.

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Depletion Mode FET Load Devices Switched with Positive Signal Voltage Levels

This driver circuit has a low capacitance input impedance and fast switching speed without increased power consumption. The basic switching circuit includes enhancement-mode output field-effect transistors (FETs) 11 and 13 and inverting FETs 15 and 17. The inverting FETs 15 and 17 isolate the input from the large gate capacitance of the output transistors.

Switched load depletion-mode transistors 19, 21 and 23 are switched by the input and clock signals which swing from +5 to zero volts. Switching of a depletion-mode device cannot be accomplished until the gate is made negative with respect to the source. The source of transistor 19 and transistor 21 or 23 is raised to +5 volts and retains this positive potential for substantial time periods because of the charge stored on the intrinsic capacitance of nodes 25 and 27. Accordingly, transistors 19, 21 and 23 can be cut off by zero-volt gate potentials.

Depletion-mode FET 29 acts as a series current source to limit current when FET 19 is conducting.

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