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Substrate PNP Transistor with High Current Gain

IP.com Disclosure Number: IPCOM000087141D
Original Publication Date: 1976-Dec-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Ayers, RL: AUTHOR

Abstract

The collector efficiency of a substrate PNP may be enhanced by disposing a P+ collector between the emitter and base contacts.

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Substrate PNP Transistor with High Current Gain

The collector efficiency of a substrate PNP may be enhanced by disposing a P+ collector between the emitter and base contacts.

The figure shows a substrate PNP device 10 including a P type substrate 12 and an N type epitaxial layer 14. A P type isolation ring 16 is disposed in the layer 14 to establish active regions 18. A P type emitter 20 and a collector 22 are formed in the active region with the collector overlapping, in part, the isolation region 16. An N type base contact 23 is formed in the region 18.

In operation the collector-base depletion regions, extending up from the substrate and down from the collector diffusion, meet or nearly meet in region 24, substantially eliminating recombination of minority carriers in the region of the base contact. This has the effect of increasing the current gain of the device 10.

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