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Programmable Logic Array with Increased Personalization Density

IP.com Disclosure Number: IPCOM000087145D
Original Publication Date: 1976-Dec-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 50K

Publishing Venue

IBM

Related People

Conrad, DA: AUTHOR [+3]

Abstract

The OR array is characterized by output diffusion rails which are parallel to the AND array input signal lines. Each OR array diffusion rail runs the width of the programmable logic array (PLA), that is, as long as there are product terms. In the case of a segmented PLA, the OR array may only run a portion of that width, there being another output diffusion rail running the rest of that width. This device eliminates completely the need for that output diffusion rail for those OR array outputs which conditionally discharge by only a single AND array output. The purpose of eliminating this OR array output diffusion rail is to decrease the area of the OR array and, therefore, to decrease the overall size of the PLA.

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Programmable Logic Array with Increased Personalization Density

The OR array is characterized by output diffusion rails which are parallel to the AND array input signal lines. Each OR array diffusion rail runs the width of the programmable logic array (PLA), that is, as long as there are product terms. In the case of a segmented PLA, the OR array may only run a portion of that width, there being another output diffusion rail running the rest of that width. This device eliminates completely the need for that output diffusion rail for those OR array outputs which conditionally discharge by only a single AND array output. The purpose of eliminating this OR array output diffusion rail is to decrease the area of the OR array and, therefore, to decrease the overall size of the PLA.

In this device, the AND array output is brought completely through the OR array, on the right hand side of the OR array as shown in the figure. There is a ground diffusion 38 which acts as the ground leg for each output circuit which requires only a single AND array output. The AND array signal terminates just beyond the ground diffusion so that a thin oxide field-effect transistor (FET) enhancement device is formed by the ground diffusion as the source, a diffusion which will serve as the output diffusion for the OR array as the drain, and the thin oxide covered by the AND array output metal line. The output diffusion rail is connected via a contact to the metal level, which serves as the OR array output. A V(DD) diffusion is juxtaposed to the right of the line of output diffusions with a thin oxide over the region between the V(DD) diffusion rail and each output diffusion. The load devices 39 thus formed are depletion load devices for the OR array.

The figure shows the AND array 10 which is comprised of a plurality of horizontal diffusion lines 12 with a first plurality connected through load devices 18 to the drain potential V(DD) and a second plurality connected to ground potential. An input signal is placed upon the metallized gate line 14 which overlies the horizontal diffusion lines 12, and every place where there is a thin oxide window 16 overlying the diffusions 12, an active FET device is formed. When the signal on line 14 is on, the channel region of the FET 16 thus formed conducts, thereby causing the horizontal diffusion connec...