Browse Prior Art Database

Timing Technique to Simulate FET Logic Delay

IP.com Disclosure Number: IPCOM000087148D
Original Publication Date: 1976-Dec-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Kirby, MD: AUTHOR [+2]

Abstract

A technique is described for correcting false time diagrams by present simulation techniques where the cut-off pulsewidth is equal to, greater than or less than the delay period, by making the logical switching coincident with the cut-off specification rather than the delay of the block. The delay is used as the reference mark for the switching.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 2

Timing Technique to Simulate FET Logic Delay

A technique is described for correcting false time diagrams by present simulation techniques where the cut-off pulsewidth is equal to, greater than or less than the delay period, by making the logical switching coincident with the cut-off specification rather than the delay of the block. The delay is used as the reference mark for the switching.

In the design verification of large-scale integration (LSI) random logic components (e.g., chips/modules), logic simulation plays a key role. In performing accurate logic simulation, the logic simulation requires, among other inputs, detailed timing specifications of various circuit elements on the chip. The timing specification of a primitive circuit function such as NOR, NAND, etc., is composed of time delay and cut-off pulse widths, propagating as well as nonpropagating. In a conventional simulator, when the input pulse width is less than or equal to the cut-off specification of the logic block, the output of the block is shown to be not switched; if the input pulsewidth is greater than the cut-off specification, the output is shown switched in time coincidence with the block delay. To illustrate, a propagating pulse is depicted in Fig. 1 for a 2-input NOR circuit. The output of the simulator is shown in the form of a timing diagram. Here the cut-off specification is assumed smaller than or equal to the block delay, which is a requirement of the simulator for proper operation. Cut-off designations start with C and delay designations start with D.

Block delays...