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Stepping Motor Control Circuit

IP.com Disclosure Number: IPCOM000087175D
Original Publication Date: 1976-Dec-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 41K

Publishing Venue

IBM

Related People

Juliana, A: AUTHOR

Abstract

A digital circuit for synchronously accelerating and decelerating a linear stepping motor is shown. With this circuit the acceleration and deceleration ramps can be digitally adjusted for the number of steps, load and speed.

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Stepping Motor Control Circuit

A digital circuit for synchronously accelerating and decelerating a linear stepping motor is shown. With this circuit the acceleration and deceleration ramps can be digitally adjusted for the number of steps, load and speed.

The circuit utilizes a shift register which is a parallel-load shift register in which data can be shifted either right or left. Digital data approximating the desired acceleration curve for the motor is loaded into the shift register in response to either a START or STOP signal. This data is then shifted in response to motor step pulses either right or left to provide signals to decelerate or accelerate the stepping motor.

Shift register 1 provides parallel load of 16 bits of digital data at terminals 2 in response to simultaneous up-level signals at terminals 3 and 4. An up-level signal to terminal 4 indicates a left shift and an up-level signal to terminal 3 indicates a right shift. The motor step pulses at terminal 30 are directed to shift clock input 5. The output signals are provided at terminals 6 and 7, and the register is reset by a signal at terminal 8.

The START or STOP signal is coupled to condition a single shot 9 whose output is used to set flip-flop 10 to the opposite state and to condition OR circuits 11 and 12. The outputs of OR circuits 11 and 12 are coupled to terminals 3 and 4 to load the digital data into shift register 1. The data could be supplied from a data processing system so that the data could be changed as desired; however, in the arrangement shown, the input data is hard-wired to produce a selected characteristic by producing a "1" bit for those positions coupled to the +V supply and a "0" bit for those positions coupled to ground. When single shot 9 is timed out, the input to OR circuit 11 or 12 is deconditioned dependi...