Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

# Netspec: Integrated Array Logic

IP.com Disclosure Number: IPCOM000087192D
Original Publication Date: 1976-Dec-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 91K

IBM

## Related People

Gardner, PL: AUTHOR [+2]

## Abstract

Netspec is an array logic technique (Fig. 1) whereby the cross points of an array of horizontal lines H1, H2, etc., and vertical lines V1, V2, etc., can be connected either through an HV cell 1 or a VH cell 2, or may be left unconnected. An HV cell 1 inverts the signal on the horizontal line H2 and dot-ANDS the output onto the vertical line V1. A VH cell 2 transfers the signal on the vertical line V1 to the horizontal line H3 without inversion.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 66% of the total text.

Page 1 of 2

Netspec: Integrated Array Logic

Netspec is an array logic technique (Fig. 1) whereby the cross points of an array of horizontal lines H1, H2, etc., and vertical lines V1, V2, etc., can be connected either through an HV cell 1 or a VH cell 2, or may be left unconnected. An HV cell 1 inverts the signal on the horizontal line H2 and dot-ANDS the output onto the vertical line V1. A VH cell 2 transfers the signal on the vertical line V1 to the horizontal line H3 without inversion.

One preferred form of array has eight horizontal and four vertical lines with VH cells (if required) at the intersections on the diagonal from a lower corner. An example of a preferred Netspec array is shown in Fig. 2. The arrangement of HV cells (squares) and VH cells (diamonds) transforms the inputs A to D into the outputs shown.

A particularly simple implementation of the preferred form Netspec array can be achieved using integrated injection logic (IIL) of which the basic element is shown in Fig. 3. The regions between contacts 3 and 4 form a lateral pn transistor. Current is injected at contact 3 and the logic input is at contact 4. Inverted outputs are taken from contacts 5.

The Netspec implementation is shown in Fig. 4. In an n type substrate is diffused a p type grid 6, which forms the emitter of all p type transistors, and p type islands 7 which form the horizontal conductors of each array and act as the collectors of the pnp transistors and the bases of the npn transistors. The inv...